Final Program

8:30-8:45	Opening Remarks: Lixin Zhang, ICT, Chinese Academy of Sciences
8:45-9:00	Program Chair's Note: Onur Mutlu, Carnegie Mellon University (PDF) (slides)
9:00-10:15	Can Parallel Data Structures Rely on Automatic Memory Managers? (slides) ISMM/MSPC Invited Talk: Erez Petrank, Technion (Bio)
10:15-10:30	Break
10:30-11:20	Session 1: Locality and Memory Models
	Session Chair: Chen Ding, Rochester Identifying Optimal Multicore Cache Hierarchies for Loop-based Parallel Programs via Reuse Distance Analysis Meng-ju Wu and Donald Yeung University of Maryland (ACM DL Link) (slides) (poster) Can Seqlocks Get Along with Programming Language Memory Models? Hans Boehm HP Labs (ACM DL Link) (slides) (poster)
11:30-12:20	Session 2: Memory Scheduling
	Session Chair: Hyesoon Kim, Georgia Tech Rank Idle Time Prediction Driven Last-Level Cache Writeback Zhe Wang, Samira Khan, and Daniel Jimenez University of Texas at San Antonio (ACM DL Link) (slides) (poster) Trace-driven Simulation of the Memory System Scheduling in Multithread application Pengfei Zhu, Mingyu Chen, Yungang Bao, Licheng Chen, and Yongbing Huang ICT, Chinese Academy of Sciences (ACM DL Link) (slides) (poster)
12:30-13:30	Break
13:30-14:45	Session 3: Memory Management
	Session Chair: Erez Petrank, Technion Parallel Memory Defragmentation on a GPU Ronald Veldema, Michael Philippsen Universitat Erlangen-Nurnberg (ACM DL Link) (slides) (poster) Analysis of Pure Methods using Garbage Collection Erik Österlund and Welf Löwe Linnaeus University (ACM DL Link) (slides) (poster) Towards Region-Based Memory Management for Go Matthew Davis, Harald Sondergaard, Peter Schachte, and Zoltan Somogyi University of Melbourne (ACM DL Link) (slides)
15:00-15:30	Break
15:30-16:15	Session 4: Poster Potpourri
	Session Chair: Hans Boehm, HP Labs A Higher Order Theory of Locality Chen Ding and Xiaoya Xiang University of Rochester (ACM DL Link) (slides) (poster) Supporting Virtual Memory in GPGPU without Supporting Precise Exceptions Hyesoon Kim Georgia Tech (ACM DL Link) (slides) (poster) A Study Towards Optimal Data Layout for GPU Computing Eddy Zheng, Zhang, Han Li, and Xipeng Shen The College of William and Mary (ACM DL Link) (slides) (poster) Design Space Exploration of Memory Model for Heterogeneous Computing Jieun Lim and Hyesoon Kim Seoul National University (ACM DL Link) (slides) (poster) Defensive Loop Tiling for Multi-core Processor Bin Bao and Xiaoya Xiang University of Rochester (ACM DL Link) (slides)
16:15-17:30	Poster Session and Wild and Crazy Idea Presentations

ISMM/MSPC Invited Talk

Can Parallel Data Structures Rely on Automatic Memory Managers?
Erez Petrank, Technion

Abstract
The complexity of parallel data structures is often measured by two major factors: the throughput they provide and the progress they guarantee. Concurrent access (and furthermore, optimistic access) to shared objects makes the management of memory one of the more complex aspects of concurrent algorithm design. The use of automatic memory management greatly simplifies the design of parallel algorithms. However, currently we do not know how to build a practical automatic memory manager that supports concurrent algorithms with progress guarantees. This talk examines the current state-of-the-art memory management support for concurrent algorithms, and spells out the most difficult open problem facing the memory management community today.

Bio
Erez Petrank is a professor of computer science at the Technion. Erez's research interests are in the areas of memory management and parallel algorithms. He has been active in designing concurrent data structures and various memory management algorithms. He also participated in the construction of practical systems at IBM and at Microsoft.